library ieee;
use ieee.std_logic_1164.all;
entity h_adder is
	port(
		a,b : in std_logic;
		co,sum : out std_logic
		);
end;

architecture behave of h_adder is
	signal abc:std_logic_vector(1 downto 0);
begin
	abc <= a & b;
	process(abc) begin
		case (abc) is
			when "00" => co <= '0'; sum <= '0';
			when "01" => co <= '0'; sum <= '1';
			when "10" => co <= '0'; sum <= '1';
			when "11" => co <= '1'; sum <= '0';
			when others => null;
		end case;
	end process;
end behave;
	